The present invention relates to methods of mounting integrated circuits on boards, to interconnect the integrated circuits in a desired macroscopic circuit configuration.
One conventional way of packaging integrated circuits (chips) is in cofired ceramic chip carriers. These carriers hermetically enclose an integrated circuit, and have metal traces (leads) which lead through the walls of the package (after it is fired) to connect internal bonding sites (from which internal leads can contact the chip bonding sites) to external contacts (which are normally at the lower edges of the chip carrier). These chip carriers have many advantages, but the technology for attaching them to the circuit board has been a limitation on their usefulness.
Conventionally, the external contacts at the bottom edges of a chip carrier have been soldered directly to traces or contact pads on a circuit board. This provides a small footprint (area of board consumed) as well as a small height, and conservation of both these dimensions is important. However, in this technology, the contacts must serve three different functions: they provide the thermal and mechanical connection of the package to the board, as well as providing the electrical connections needed. It is not possible to optimize all three of these functions in this contact structure, and several difficulties result. A further limitation of this technology is that it is not well suited to placing contacts other than at the edge of the package.
As semiconductor device lead counts have increased and higher density packaging has become a necessity, packaging concepts have been shifting from perimeter connections in the form of solder joints or rigid leads to more dense array style connections. Also, surface mounting, as opposed to the through-hole approach, has been widely accepted as the most effective way of achieving lower profiles and higher board routing densities. However, there are many problems associated with surface mounting an array style package. These are in addition to existing problems with conventional perimeter style surface mounting of leadless chip carriers. The present invention eliminates many of these problems and alleviates others (most importantly the inspectability problem) and can be used on custom pad grid array packages as well as JEDEC standard perimeter pad leadless chip carriers.
The present invention teaches a novel method and structure for attaching a chip carrier (e.g. a cofired ceramic pad grid array package, or a standard leadless chip carrier (LCC) with contacts around its lower edges only) to a circuit board. The chip carrier may be of the type having a body composed of multilayered fused ceramic. Furthermore, the chip carrier may include, for example, a body fired from three or more layers of alumina, with the first level interconnect (from die to chip carrier) made using TAB technology or more conventional wire bonding, and with a Kovar lid soldered on to effect a hermetic seal. The underside of the chip carrier may have, for example, an array of gold plated pads (a pad grid configuration), or may have more conventional perimeter contacts; but in the center of the underside the present invention teaches that a thermally conductive spacer block should be used.
This spacer block does not have to be an electrical insulator. For example, a small molybdenum block brazed onto the underside of the chip carrier is a preferred embodiment of this spacer. The spacer block provides the primary mechanical attachment between the chip carrier and the board, and also serves as a thermal spreader to aid in the dissipation of the heat generated by the chip. The spacer block may be initially attached to the chip carrier or initially attached to the board; but what is important is that the mechanical and thermal connections can now be performed separately from the electrical connection.
The electrical connection is preferably performed by an adaptation of TAB technology. The technique known as TAB (Tape Automated Bonding) has previously been used to attach bonding leads to chips. In this technique a flexible sheet (e.g. of polyimide) carries a number of conductive traces which are bonded to the bond pads on an integrated circuit at one end, and bonded to (for example) the bonding sites on the interior bonding shelf of a chip carrier containing the chip at the other end. Typically the TAB strip will have a hole in its middle for the chip, and will have traces extending outward more or less radially from the perimeter of this hole to the outer edge of the TAB strip. Where contacts are to be made, the traces may extend somewhat beyond the polymer supporting sheet.
The present invention teaches that electrical connections from the chip carrier to the circuit board should be made, separately from the thermal and primary mechanical connections, by using a modification of TAB technology. The chip carrier is connected to the board by connecting strip, which is a very thin sheet of polymer (e.g. polyimide) with a network of copper traces photographically etched on one or both faces. The connecting strip is attached to the array of pads on the underside of the chip carrier by any of several possible methods. The assembly (chip carrier with spacer block and connecting strip attached) is then aligned on the board, and the spacer block is attached to the board using solder, RTV (room-temperature vulcanizer, i.e. rubber cement) epoxy, or other method. Finally, the connecting strip is connected to matching pads on the board (preferably by soldering, to permit rework if necessary).
Note that the power traces in the connecting strip can have different widths or thicknesses from the signal traces, and that some rudimentary routing (distribution) is possible by extending or curving the traces on the connecting strip. That is, with the present invention it is not necessary for all the connecting strips to terminate approximately the same distance from the chip.
It should also be noted that other electrical connection technologies could be substituted for the connecting strip technology described here. That is, one of the key teachings of the present invention is that the thermal connection and electrical connection from chip carrier to board should follow separate paths, and many advantages derive from this separation. Moreover, although some mechanical support may be derived frpm the tensile strength of the connecting strip, the primary mechanical support is also separated from the electrical connection structure; and this is another generally applicable teaching of the invention, which can be used without using the specific connecting strip technology describe here as preferable.
A few of the key advantages resulting from this novel configuration will now be discussed.
Major criteria in any packaging configuration include inspectability, testability, and stability over thermal cycling. The present invention provides major advantages in all these areas, including at least the following:
The present invention provides an assembly which is fully testable and available for qualification at the sealed package level. The sealed chip carrier can be connected to a reasonably conventional burn-in socket before the connecting strip is attached, or test fixtures which will contact the traces on the connecting strip could be used for testing after the connecting strip has been attached. PA0 Test clips can, in many applications, be more easily applied to a chip carrier mounted on board. The connecting strips will typically reach out to make contact to the board beyond the edge of the chip carrier, whereas in the prior art the connection points between chip carrier and board would be right at the edge of the carrier, and thus it would be difficult to reach exactly along the walls of the chip carrier to reach the solder joints. PA0 Second level interconnections at the chip carrier end and the board end are completely inspectable. This has been a major stumbling block in the development of space-saving array style packages. That is, the interconnections between the connecting strip and the carrier can be easily inspected before the carrier is mounted to the board, and the interconnections between the connecting strip and the board can be easily inspected after the carrier is mounted to the board. PA0 The present invention provides greater flexibility in board layout than is permitted by standard leadless chip carriers or other surface mountable packages. Since the locations of electrical connections are not dictated by structural needs they can be located at the location which is electrically most advantageous, since routing can be done on the connecting strip to extend a trace to a convenient location. PA0 Power and ground leads on the connecting strip can be increased in width, to provide a low resistance connection from the chip carrier to the board. PA0 The interconnects are inherently electrically efficient. The copper used as the electrical conductor has a very low resistivity and the polyimide has a very low dielectric constant. PA0 The overall package configuration has a low physical profile, equal to or less than that of any other surface mount configuration. The height required for the spacer block under the chip carrier will in some embodiments be no more than the clearance caused by the solder bumps under a conventionally mounted leadless chip carrier package. PA0 The present invention allows very high density packaging--the output pad array on the underside of the chip carrier could be spaced as densely as 0.025 inch centers using existing technology, and closer spacings will be possible in future production technology. PA0 The configuration of the present invention is more reworkable than a standard surface mountable package. Less heat will be required to reflow the solder, since PA0 The problem of solder joints breaking due to shear forces (generated under thermal cycling by thermal coefficient of expansion (TCE) mismatch between board and chip carrier) is greatly reduced, for several reasons. PA0 Since the mechanical connections are not held by solder, stronger materials can be used. This is particularly advantageous in environments which may combine high temperatures, vibration, and lateral acceleration. PA0 The present invention is applicable to a wide variety of board technologies. Moreover, since the requirements of thermal match between chip carrier and board are eased, it may now be possible to use board constructions which have good thermal conductivity, good mechanical strength, and good electrical routing properties, but which were not previously practicable due to thermal expansion mismatch. Moreover, it may now be possible to eschew some of the very expensive sandwich-structured board compositions which have been used to achieve an acceptable thermal match.
(1) the joints are easily accessible, and PA1 (2) the connecting strip thermally isolates the joint from the chip carrier which, under normal circumstances, acts as a heat sink. PA1 (1) In the present invention, the electrical connections are not exposed to these shear forces at all. PA1 (2) In the present invention, direct TCE match from chip to board is not as critical: instead, this strain-generating interface is separated into two parts, namely carrier-to-spacer and spacer-to-board. Thus, if the spacer is chose from a material which has a TCE intermediate between the carrier and the board, the strain generated at each interface is reduced. PA1 (3) Even for a given degree of TCE mismatch, less shear force is generated, since the spacer is not as wide as the carrier. PA1 (4) The spacer block provides a stronger structural mount than typical solder joints.
According to the present invention there is provided: A circuit board comprising: a substrate; a plurality of chip carriers mounted on said circuit board substrate; and a plurality of traces on said circuit board interconnecting said chip carriers in the desired macroscopic electrical circuit configuration; at least some of said chip carriers being mechanically connected to said board by a thermally conductive spacer block which is attached to the underside of said chip carrier but is smaller than said chip carrier, electrical connection between said chip carrier and said board traces being made by a connecting strip having a plurality of metallic traces thereon.